1. Technical Field
The present application generally relates to fine-tuning techniques for power supplies, the techniques are based on voltage drop measurements, and find use in, for example, System-on-a-Chip (SoC) architectures for mobile applications.
The techniques also find applications in mobile devices, such as mobile (cell) phones, smart phones, tablets, laptops, etc.
2. Related Art
The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Power consumption has become a key factor in determining the limits of the performance of integrated circuits, especially in respect of devices intended for use in mobile devices.
Generally, in integrated circuits for use in mobile devices, such as smart-phones, tablets and laptops, there is a trade-off between the battery-life and the processing performance of the integrated circuit. This is because an increase in processing performance will typically result in an increase in the power consumption, and hence a reduction in the lifetime of the battery that is used to power the circuit.
To address this issue, the power consumption for a given processing performance can be improved by adopting low power integrated circuit designs, for example by adopting technology that allows circuits to operate at a low voltage. As disclosed in [ITRS 2011, http://www.itrs.net/home.html], very low power design (VLPD) technology, employs methods to both reduce the power consumption and also a system of power-tuning that depends on the desired performance. Thus, for example, the power supplied to an integrated circuit using VLPD can be adjusted to suit the processing that the circuit is currently carrying out (i.e., dependent on the application that is being executed).
A further method of reducing power consumption is the Dynamic Voltage Frequency Scaling (DVFS) approach. This is described, for example, in [M. Horowitz, T. Indermaur, and R. Gonzalez, “Low-power digital design,” IEEE Symp. On Low Power Electronics, 1994, pp. 8-11].
DVFS technology employs pre-defined operating conditions (OPs) which scale the supplied voltage and frequency dependent on the needs of the current OPs. DVFS employs predefined fixed values of the voltage and frequency for different OPs, and so the power cannot generally be fine-tuned depending on the particular application that is running.
To improve the accuracy of the power-tuning, a closed loop control system called Adaptive Voltage Scaling (AVS) approach has been proposed in [S. Dhar, D. Maksimovic, and B. Kranzen, “Closed-loop adaptive scaling controller for standard-cell ASICS,” ISLPED 2002, pp 0.103-107]. This technique permits continuous adaptation of the supplied voltage/frequency via the closed loop control. However, the level of accuracy achieved is dependent on the accuracy of the measurement of the actual power consumption.
The process monitoring box (PMB) disclosed in [Chakravarty S., et al, “Optimal Manufacturing Flow to Determine Minimum Operating Voltage”, Electronic Design, Monterey, Calif., Aug. 12-14, 2002, pp. 103-107, [ITC 2011, pp. 1-10]] can be used to determine the optimal operating voltage in a production flow. PMB is represented as a ring oscillator, whose output is used as the clock of a counter. This counter counts for a fixed length of time and that count can be read out as a value, C. C is used as a correlation factor to determine the optimal operating conditions. PMB based predictions of die parameters are strongly dependent on the number of stages used in the ring oscillator. Therefore, a compensation factor has to be added into the correlation factor.
In [S. Dhar, D. Maksimovic, and B. Kranzen, “Closed-loop adaptive scaling controller for standard-cell ASICS,” ISLPED 2002, pp 0.103-107], a voltage supply regulation scheme based on embedded delay line is disclosed. The controller is composed of delay line elements, level shifters and capture elements (flip-flops). The controller allows a fast transient response to step changes in speed, and also allows operation over a range of system clock frequencies. However, this solution suffers from low precision in terms of power supply noise consideration, when activity in the circuit is present, due to the reduced controller operating frequency that is employed.
A European patent application EP12305986.7, filed on the same day as this application by the applicant, Valka, M. et al., “Efficient Power Measurement Based on Timing Uncertainty,” C03195, 8 Aug. 2012, ST-Ericsson SA discloses a method of measuring power supply noise in an integrated circuit based on a timing uncertainty in a clock signal. This application is not prior art for the present application, and the power supply noise measurement device and method disclosed therein is employed in the present application as part of a voltage control system. Accordingly, document EP12305986.7 is herein incorporated by reference in its entirety.